1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a patterning method and a method for fabricating a dual damascene opening.
2. Description of Related Art
Along with rapid progress of semiconductor technology, the dimensions of semiconductor devices are reduced and the integrity thereof promoted continuously to further advance the operating speed and performance of integrated circuits (ICs). In general, as the semiconductor devices develop towards the design of the compact circuits, the lithography process plays a significant role in the entire process. In the semiconductor process, for the patterning of each film or areas with implanted dopant, the scope thereof is defined and the critical dimension (CD) is determined by the lithography process. Patterns are generally formed in a photoresist layer through the lithography process. A dry etching process or a wet etching process is then performed with the photoresist layer employed as an etching mask, so that the patterns in the photoresist layer are transferred to a layer to be patterned thereunder.
As the devices are continuously miniaturized and integrated, the design of the ICs becomes increasingly complicated, such that accuracy of the pattern transferring is quite important. The CD of the patterns is gradually reduced, and thereby the lithographic process requires high resolution correspondingly. To meet the requirement of high resolution, the thickness of the photoresist layer has to be thinned down. During the subsequent etching process, the photoresist layer with insufficient thickness as an etching mask, however, is very likely to be consumed thoroughly before the patterns are completely transferred to the underlying layer to be patterned, so that the desired patterning function cannot be accomplished.
Moreover, as the demand for the device integrity is raised, dramatic changes in physical properties have to be considered so as to avoid a great impact on the operating speed and performance of the devices. As shown in FIG. 1, taking a pattern transferring with use of a patterned photoresist layer (not shown) as an example, openings 104 are formed in a layer 102 to be patterned which is on a substrate 100. After performing an etching process, the openings 104 may suffer from excessively large top CD if the patterns of the adjacent openings 104 are too close. When a conductive layer 106 is deposited in the openings 104, the conductive structures formed in the adjacent openings 104 are prone to bridging 108 therebetween, which may seriously impact the subsequent process and product reliability. In addition, the opening patterns of the patterned photoresist layer tend to form bowing profiles, each of which has a wider center and a narrower top and bottom, due to over side etching of the patterned photoresist layer. Accordingly, after the patterns of the patterned photoresist layer are transferred to the layer 102 to be patterned, the openings 104 formed in the layer 102 to be patterned are easily obtained with the bowing profiles 110.
As a result, how to meet the purpose of improvement in the bridging and bowing profile defects of the openings is one of the immediate issues to be solved in the art as CD of the patterns is miniaturized, so as to ensure the device reliability and yield in the subsequent process.